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| 256Kx16 Multiplexed STRAM Document Title 256K x 16Bit Multiplexed Single Transistor RAM EM742SP16 Revision History Revision No. 0.0 0.1 0.2 0.3 0.4 History Initial Draft 1'st Revision 2'nd Revision 3'rd Revision 4' th Revision Add to pad coordinate Product code chang from EM742SP16AW to EM742SP16 Valid address change from A18 to A17 Remove configure register sets at functional descripition table Draft Date December 21 , 2006 March 07, 2007 March 20, 2007 March 28, 2007 May 9, 2007 Remark Preliminary Preliminary Preliminary Priliminary Priliminary 4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com Emerging Memory & Logic Solutions Inc. Zip Code: 690-717 The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1 256Kx16 Multiplexed STRAM EM742SP16 256K x16 Bit Multiplexed Single Transistor RAM FEATURES - Process Technology : 0.13m CMOS process - Organization :256K x16 - Power Supply Voltage : 1.7~1.9V - Multiplexed address and data bus - Three state outputs - Auto TCSR for power saving GENERAL WAFER SPECIFICATIONS - Deep trench process - 3 Metal layers including local inter-connection - Wafer diameter : 8-inch PAD DESCRIPTION Name /CS /OE /WE /AVD ADQi Ai Function Chip select inputs Output enable input Write enable input Address valid input Address/Data In-out Address inputs Name /LB /UB VCC VCCQ Function Lower byte (ADQ0~7) Upper byte (ADQ8~15) Power supply I/O Power supply VSS(Q) Ground NC No connection FUNCTION BLOCK DIAGRAM /AVD /CS /UB /LB /WE /OE Self-Refresh CONTROL CONTROL LOGIC COLUMN SELECT ROW SELECT A16~A17 ADDRESS DECODER Memory Array 256K X 16 ADQ0~ ADQ15 ADDRESS/DATA Multiplexer Din/Dout BUFFER I/O CIRCUIT 2 256Kx16 Multiplexed STRAM ABSOLUTE MAXIMUM RATINGS 1) Parameter Voltage on Any Pin Relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage Temperature Operating Temperature EM742SP16 Symbol VIN, VOUT VCC, VCCQ PD TSTG TA Minimum -0.2 to VCCQ+0.3V -0.22) to 2.5V 1.0 -65 to 150 -25 to 85 Unit V V W oC oC 1. Stresses greater than those listed above "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Undershoot at power-off : -1.0V in case of pulse width < 20ns FUNCTIONAL DESCRIPTION CS H L L L L L L L L L OE X H X H L L L H H H WE X H X H H H H L L L LB X X H H L H L L H L UB X X H H H L L H L L AVD X H X L H H H H H H ADQ0~15 High-Z High-Z High-Z Add. Input Data Out Data Out Data Out Data In Data In Data In A16~A17 X X X Add. Input X X X X X X Mode Deselected Output Disabled Output Disabled Address Input Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Stand by Active Active Active Active Active Active Active Active Active Note: X means don't care. (Must be low or high state) 3 256Kx16 Multiplexed STRAM RECOMMENDED DC OPERATING CONDITIONS 1) Parameter Supply voltage Ground Input high voltage Input low voltage 1. 2. 3. 4. EM742SP16 Symbol VCC VCCQ VSS, VSSQ VIH VIL Min 1.7 1.7 0 VCCQ - 0.4 -0.23) Typ 1.8 1.8 0 - Max 1.9 1.9 0 VCCQ + 0.22) 0.4 Unit V V V V V TA= -25 to 85oC, otherwise specified Overshoot: VCC +1.0 V in case of pulse width < 20ns Undershoot: -1.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f =1MHz, TA=25oC) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled, not 100% tested Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 10 Unit pF pF DC AND OPERATING CHARACTERISTICS Parameter Input leakage current Output leakage current Symbol ILI ILO ICC1 Average operating current ICC2 Output low voltage Output high voltage VOL VOH ISB1 Test Conditions VIN=VSS to VCCQ , VCC=VCCmax CS=VIH or OE=VIH or WE=VIL , VIO=VSS to VCCQ , VCC=VCCmax Cycle time=1s, 100% duty, IIO=0mA, CS<0.2V, VIN<0.2V or VIN>VCCQ-0.2V Cycle time = Min, IIO=0mA, 100% duty, CS=VIL, VIN=VIL or VIH IOL = 0.1mA, VCC=VCCmin IOH = -0.1mA, VCC=VCCmin CS>VCCQ-0.2V, Other inputs = 0 ~ VCCQ (Typ. condition : VCC=1.8V @ 25oC) (Max. condition : VCC=1.9V @ 85oC) Min -1 -1 VCCQ-0.1 Typ - Max 1 1 3 25 0.1 - Unit uA uA mA mA V V Standby Current (CMOS) LL - - 60 uA 1. Maximum Icc specifications are tested with VCC = VCCmax. 4 256Kx16 Multiplexed STRAM AC OPERATING CONDITIONS EM742SP16 Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.2V to VCCQ-0.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : VCCQ/2 Output Load (See right) : CL = 30pF 1. Including scope and Jig capacitance 1) Dout CL1) AC CHARACTERISTICS (Vcc = 1.7 to 1.9V, Gnd = 0V, TA = -25C to +85oC) Parameter List AVD Low pulse Common Address setup to AVD rising edge Address hold from AVD rising edge Chip enable setup to AVD rising edge AVD low to data valid time Address access time Chip enable to data output Address disable to output enable Output enable to valid output Read UB, LB enable to data output UB, LB enable to low-Z output Output enable to low-Z output Chip disable to high-Z output UB, LB disable to high-Z output Output disable to high-Z output AVD low to end of write Address valid to end of write Chip enable to end of write Write Write pulse low UB, LB valid to end of write Data to write time overlap Data hold from write time Symbol tAVD tAVDS tAVDH tCSS tACC1 tACC2 tACC3 tADOE tOE tUBLBA tBLZ tOLZ tHZ tBHZ tOHZ tACW1 tACW2 tACW3 tWRL tBW tDW tDH Speed Min 15 15 5 7 0 5 5 70 70 70 45 50 25 0 Max 1000 70 70 70 25 25 15 15 15 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 256Kx16 Multiplexed STRAM Device Operaton The access is performed in two stages. The first stage is address latching. The first stage take place between point A and B in timing diagram. At this stage, the Chip Select(CS) to the device is asserted. The random access is enabled either from the point the address becomes stable, the falling edge of the AVD signal or from the falling edge of the last chip select signal. The second stage is the read or write access. This takes place between points B and C in timing diagram. In case of a read access, the multiplexed address/data bus (ADQ0 ~ ADQ15) changes its direction. It is important to notice tOE when it is dominant that the device gets into the read cycle since the address is available long before the device output is enabled. EM742SP16 Read Access The read access is initiated by applying the address to the multiplexed address/data bus or to the address bus over A15 (A16 -> Axx). When the address is stable, the device chip select(CS) is set active low. At point A, the AVD signal is taken low and the latch becomes transparent. This allows the address to be propagated to the memory array. The address is stable at the rising edge of the AVD signal. The AVD signal goes high at point B in which the address latch is completed. At this point the read cycle is entered. The OE signal is set active low. This changes the direction of the bus. The status of control signals UB and LB are set according to the access. Data is read at point C. TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE (1) ( WE = VIH ) A tAVD B C AVD tAVDS Address/Data Address Valid tACC1 tAVDH Data Valid tACC2 tADOE tOLZ tOHZ tOE tHZ OE tCSS tACC3 CS tBLZ tBHZ UB, LB tUBLBA 6 256Kx16 Multiplexed STRAM EM742SP16 TIMING WAVEFORM OF READ CYCLE (2) ( WE = VIH ) A tAVD B C AVD tAVDS Address/Data Address Valid tAVDH Data Valid tACC2 tOLZ tOHZ tOE tHZ OE tCSS CS tBLZ tUBLBA tBHZ UB, LB NOTES (READ CYCLE) 1. tHZ and tBHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 7 256Kx16 Multiplexed STRAM Write Access The write access is initiated by applying the address to the multiplexed address/data bus or to the address bus over A15 (A16 -> Axx). When the address is stable, the device chip select(CS) is set active low. At point A, the AVD signal is taken low and the latch becomes transparent. This allows the address to be propagated to the memory array. The address is stable at the rising edge of the AVD signal. The AVD signal goes high at point B in which the address latch is completed. At this point, the second stage of the write process is entered. Data is input to the multiplexed address/data bus. The WE signal is set low and control signal UB and LB are set according to the access. EM742SP16 TIMING WAVEFORM OF WRITE CYCLE (1) (OE = VIH) A tAVD B C AVD tACW1 tAVDS Address/Data Address Valid tAVDH Data Valid tACW2 tWRL tDW tDH WE tCSS tACW3 CS tBW UB, LB TIMING WAVEFORM OF WRITE CYCLE (2) (OE = VIH) A B tAVD C AVD tAVDS Address/Data Address Valid tAVDH Data Valid tACW2 tWRL tDW tDH WE tCSS CS tBW UB, LB NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWRL) of low CS, low WE and low UB or LB. A write begins at the last transition among low CS and low WE with asserting UB or LB low for single byte operation or simultaneously asserting UB and LB low for word operation. A write ends at the earliest transition among high CS and high WE. The tWRL is measured from the beginning of write to the end of write. 8 256Kx16 Multiplexed STRAM TIMING WAVEFORM OF POWER UP 200us VCC(Min.) EM742SP16 VCC CS Power Up Mode Normal Operation NOTE . ( POWER UP ) 1. After Vcc reaches Vcc(Min.) , wait 200us with CS high. Then you get into the normal operation. TCSR (Temperature Cotrolled Self Refresh) The 4M STRAM can be operated with temperature controlled self-refresh. The device internal self-refresh period is controlled according as temperature change automatically. 9 256Kx16 Multiplexed STRAM EM742SP16 MEMORY FUNCTION GUIDE EM X XX X X X XX X X - XX XX 1. EMLSI Memory 2. Device Type 3. Density 4. Option 5. Technology 6. Operating Voltage 1. Memory Component 2. Device Type 6 ------------------------ Low Power SRAM 7 ------------------------ STRAM 3. Density 1 ------------------------- 1M 2 ------------------------- 2M 4 ------------------------- 4M 8 ------------------------- 8M 16 ----------------------- 16M 32 ----------------------- 32M 64 ----------------------- 64M 4. Function 0 ----------------------- Dual CS 1 ----------------------- Single CS 2 ----------------------- Multiplexed 5. Technology Blank ----------------- CMOS F ------------------------ Full CMOS S ------------------------ Single Transistor 6. Operating Voltage Blank ------------------ 5V V ------------------------- 3.3V U ------------------------- 3.0V S ------------------------- 2.5V R ------------------------- 2.0V P ------------------------- 1.8V O ------------------------- 1.5V 11. Power 10. Speed 9. Packages 8. Version 7. Organization 7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit 8. Version Blank ----------------A ----------------------B ----------------------C ----------------------D ----------------------E ----------------------Mother die First version Second version Third version Fourth version Fifth version 9. Package Blank ----------------- Package W ----------------------- Wafer 10. Speed 45 ---------------------- 45ns 55 ---------------------- 55ns 70 ---------------------- 70ns 85 ---------------------- 85ns 90 ---------------------- 90ns 10 --------------------- 100ns 12 --------------------- 120ns 11. Power LL --------------------- Low Low Power L ---------------------- Low Power S ---------------------- Standard Power 10 |
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